1. Field of the Invention
This invention relates generally to integrated circuit design and, in particular, to a technique for viewing a Register Transfer Level (RTL) graphical representation of an initial design synthesis.
2. Description of the Related Art
For the design of digital circuits on the scale of VLSI (Very Large Scale Integration) technology, designers often employ computer-aided techniques. Standard languages known as Hardware Description Languages (HDLs), have been developed to describe digital circuits, to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the RTL, or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing circuits using HDL compilers, designers first describe circuit elements in HDL source code and then compile the source code to produce synthesized RTL netlists. The RTL netlists correspond to schematic representations of the circuit elements. The circuits containing the synthesized circuit elements may or may not be optimized to improve timing relationships and eliminate unnecessary or redundant logic elements. Such optimization typically involves substituting different gate types or combining and eliminating gates in the circuit, and often results in re-ordering the hierarchies and relationships between the original RTL objects and the underlying source code that produced the RTL objects.
The processing time to display the RTL view grows in line with the size of a circuit design, e.g., the total number of nodes and pins. To minimize the processing time, large circuit designs are often partitioned into smaller segments prior to display. Typically, RTL displays of large circuit designs will show only one of the multiple segments, thus avoiding long processing times for the RTL view display. However, the connections for the multiple segments must somehow be accessible to the designer when navigating between the segments. Currently, the automated viewers of existing tools do not differentiate between related pages. Thus, the related page list cannot be differentiated between the source page and other destination pages. Without this differentiation between the source pages and destination pages, it makes navigating difficult when the user wants to view solely the source nodes or the destination nodes.
As a result, there is a need to solve the problems of the prior art to differentiate between related pages in order for a designer to quickly navigate to a desired source or destination.